The present invention relates to a floating gate-type non-volatile semiconductor memory of MOS structure, and more particularly, to a non-volatile semiconductor memory capable of writing electric charges in a floating gate electrode with a low voltage and a high injection efficiency.
Conventionally, a writing (injecting electric charges into a floating gate electrode) voltage of a floating gate-type non-volatile semiconductor memory using a channel injection method is generally no less than 15 V. And even in an improved memory, a writing voltage of no less than 7 V is required. In accordance with the unification of an operation voltage of a circuit system to 5 V, the requirement for a non-volatile semiconductor memory capable of being written and read at 5 V has been on the rise.
FIG. 1 shows a sectional view of a conventional floating gate-type non-volatile semiconductor memory capable of being written by channel injection at around 7 V. An n.sup.+ source region 2 and an n.sup.+ drain region 3 are formed on a P-type silicon semiconductor substrate 1 (a P-well formed on a n-type substrate can also be used), and the source and drain regions are connected to the outside by electrodes 8 and 9. The source region 2 and drain region 3 define therebetween a channel region having a first channel region portion l.sub.1 and a second channel region portion l.sub.2, the two channel region portions l.sub.1 and l.sub.2 contacting one another in between the source and drain regions. On the drain region 3 and on the channel region portion l.sub.2 contiguous to the drain region 3 is formed a floating gate electrode 6 made of poly-crystal silicon through a thin (e.g. 100 .ANG.-200 .ANG.) gate oxide film 5 and electrically isolated by an oxide film 10. On the channel region portion e.sub.1 which is in contact with the source region 2 is formed a selective gate electrode 7 through a gate oxide film 4.
The electric potential V.sub.F of the floating gate electrode 6 is controlled by the drain voltage V.sub.D applied to the drain region 3 by electrostatic capacitance coupling between the drain region 3 and the floating gate electrode 6. In case no electrons are fed to the floating gate electrode 6, for example, the electric potential V.sub.F of the floating gate region 6 becomes at around 7 V by applying V.sub.D =7 V to the drain region 3. Accordingly the surface electric potential .phi.SF of the channel region under the floating gate electrode 6 approaches the electric potential of the drain region 3. On the other hand, when a voltage almost equivalent to the threshold voltage of the selective gate electrode 7 is applied, the surface electric potential .phi.SS of the channel region under the selective gate electrode 7 becomes almost equivalent to the electric potential of the source region 2. The surface electric potential .phi.S steeply changes from .phi.SS to .phi.SF near the channel region under the border of the selective gate electrode 7 and the floating gate electrode 6. At this time, electrons are accelerated in the electric field to become hot electrons and jump into the floating gate electrode 6. The electrons can be injected into the floating gate electrode 6 only when the surface electric potential difference .DELTA..phi.S is larger than the electric potential barrier 3.2 V between the silicon substrate 1 and the silicon oxide film 5 and the surface electric potential .phi.S steeply changes.
FIG. 2 shows an example of the distribution of the surface electric potential .phi.S of the memory shown in FIG. 1 when in the writing mode. Regions I, II, III and IV corresponds respectively to the source region 2, the channel region portion l.sub.1 under the selective gate electrode 7, the channel region portion l.sub.2 under the floating gate electrode 6, and the drain region 3. The solid line indicates the distribution of the surface electric potential .phi.S in the case where the impurity density of the P-type substrate 1 is high. It shows that there exists a drop of the surface electric potential .phi.S in the region III near the region IV. The drop of the surface electric potential .phi.S is caused by the electric potential of the floating gate electrode 6 being incapable of sufficiently inverting the surface thereunder if the impurity density of the substrate 1 is high. The surface electric potential difference or drop .DELTA..phi.S at the border of the region II and the region III becomes smaller by a reduction of the surface electric potential .phi.S, which results in disturbance of a reduction in the writing voltage. The broken line shows the distribution of the surface electric potential .phi.S in the case where the impurity density of the P-type substrate 1 is low. No drop of the surface electric potential .phi.S in the region III is found and the variation of the potential .phi.S in the region II is relaxed, whereby the probability of generating hot electrons with high energy becomes smaller.
As illustrated, a reduction in the writing voltage is difficult in the conventional non-volatile semiconductor memory.